A Low Cost Parallel Scalable FPGA Architecture for Regular and Irregular LDPC Decoding

F. Verdier, D. Declercq
IEEE Transations on Communications, Volume 54, Number 7, page 1215--1223 - July 2006

BibTex references

@Article{VD06,
  author       = "Verdier, F. and Declercq, D.",
  title        = "A Low Cost Parallel Scalable FPGA Architecture for Regular and Irregular LDPC Decoding",
  journal      = "IEEE Transations on Communications",
  number       = "7",
  volume       = "54",
  pages        = "1215--1223",
  month        = "July",
  year         = "2006",
  key          = "Verdier 06",
  url          = "http://publi-etis.ensea.fr/2006/VD06"
}

Other publications in the database

» F. Verdier
» D. Declercq